An Extensive Analysis of RISC-V Floating-Point Units: Architectures, Difficulties, and Prospects

Abstract

Floating-point computation is a fundamental aspect of scientific, engineering and artificial intelligence workloads today. As an open-source, modular and extensible instruction set architecture (ISA), the RISC-V has been driving innovation in floating-point unit (FPU) design. From most simple of scalar FPUs for embedded systems to highly capable of vector FPUs for high performance computing, communications, and security applications, a wide variety of FPUs have been proposed. Despite significant advancements, however, there is still no systematic description of the design space, optimizations, and trend for RISC-V FPUs. This paper addresses this void and provides a detailed overview about RISC-V FPUs from different angles. First, the presentation discusses the floating-point formats and new numerical systems like FP8, bfloat16, Posit, and Block floating-point and their importance in terms of energy and accuracy. Second, the evolution of RISC-V FPUs from scalar to trans precision and vectorised pipelines, and special-purpose hardware for particular applications. Third, integration strategies such as tightly coupled, moderately coupled, loosely coupled, and vector-lane distributed FPUs are compared in terms of performance, modularity, and energy efficiency. Finally, the use of RISC-V FPUs in areas such as AI/ML, IoT, communications, graphics, and cryptography is examined. The paper concludes by identifying open challenges and emerging trends, such as heterogeneous FPUs, chiplet-based integration, and security-aware floating-point designs. Furthermore, RISC-V-enabled multi-FPGA platforms for event-driven Spiking Neural Network (SNN) simulation broaden the applicability of RISC-V floating-point and neuromorphic co-design toward ultra-low-power edge intelligence.