Quantum-Inspired Reconfigurable VLSI Architecture for High-Performance Computing in Deep Neural Networks

Abstract

The rapid escalation in computational demands of deep neural networks (DNNs) has exposed significant limitations in conventional CMOS-based accelerators, particularly in terms of scalability, power efficiency, and parallel processing throughput. This work proposes a Quantum-Inspired Reconfigurable VLSI Architecture (QIR-VLSI) designed to emulate quantum-like superposition, entanglement-assisted parallelism, and probabilistic weight transformations within classical hardware. The architecture integrates a hybrid Q-Gate Reconfigurable Processing Array (Q-RPA) and Stochastic Interference-Based Memory (SIBM) to dynamically adapt compute paths, enabling efficient matrix multiplication, activation approximation, and accelerate learning-based inference. A Quantum Spin-State Mapping Unit (QSMU) ensures energy-aware probabilistic feature encoding, while a Reconfigurable Weighted Path Generator (RWPG) improves sparsity utilization and fault tolerance. Fabricated on a 28-nm technology node, the proposed design achieves up to 38.7% lower power consumption, 2.94× improvement in throughput, and 1.81× area efficiency compared to state-of-the-art FPGA-based DNN accelerators when tested across benchmark workloads including CIFAR-10, ImageNet, and Tiny-YOLO inference tasks. Experimental results validate the feasibility of quantum-inspired hardware mechanisms in enhancing classical VLSI accelerators, establishing QIR-VLSI as a promising architecture for next-generation AI accelerators and edge-intelligent systems.