A Survey on Optimised Parallel Architectures for RSA Cryptographic Implementations on FPGA and ASIC

Abstract

Although the RSA public-key cryptosystem is one of the most widely used asymmetric encryption algorithms for securing digital communications, the computational complexity associated with large-integer modular exponentiation makes it difficult to implement for real-time and resource-constrained applications. This paper provides a detailed overview of optimised architectures for implementing RSA cryptographic functions on FPGAs and ASICs. The three interconnected research streams, namely, hardware-accelerated implementations of RSA on FP-GAs and ASICs, algorithmic optimisations for accelerating mod-ular exponentiation based on Chinese Remainder Theorem (CRT) and parallel software-level implementations of modular exponen-tiation in multi-core and GPU environments are systematically reviewed. The mathematical underpinnings of these optimisations are also discussed, such as Multidimensional CRT, Gaussian inte-ger based modulo samplers and robust reconstruction algorithms. Twenty primary research works from 2000 to 2026 are analyzed and key performance trends, architectural trade-offs, and open research challenges are identified. A comparison of reported implementations is given to inform future design choices in this area.