Optimized Pipelined RISC-V Processor with Data Hazard Detection for Verification of Ethernet Controller

Abstract

High-speed networking systems require more and more embedded SoC (System-on-Chip) architectures for real-time packet processing and protocol translation. However, intense data streaming often causes instruction pipeline pauses that impose tight performance constraints when integrating open-source RISC-V processors with media access control (Ethernet MAC) cores. In this study, we propose the design and FPGA implementation of an Optimized Pipelined RISC-V Processor, designed as a high throughput controller for Ethernet networking environment. It has an optimized 32-bit five stage in-order execution pipeline core with RV32I base instruction set support. The Dedicated Hardware Data Hazard Detection and Forwarding Unit is firmly connected into the execution stages to avoid the CPU bottleneck during high frequency Direct Memory Access (DMA) and Ethernet operations. To improve instruction throughput while preserving low hardware complexity, the suggested solution uses a pipelined data path based on the RV32I instruction set. Additionally, FPGA-specific optimizations are used to improve timing performance while lowering area and power consumption, such as the use of block RAM resources and efficient logic mapping. Further a robust, coverage-driven verification environment developed for an FPGA-based design using SystemVerilog. The effectiveness of the proposed framework is verified against recent state-of-the-art literature. Comparative analysis demonstrates that the proposed work achieved 100% of functional coverage while existing implementations utilizing SystemVerilog structures achieve limited coverage ranging from 90.12% to a maximum of 94.44%. The processor was implemented and evaluated on FPGA platforms of Artix-7 XC7A200T and ZYNQ XC7Z020. Experimental results show that the proposed design can run with a maximum operational frequency of 119.5 MHz on Artix-7 XC7A200T FPGA and 156.37 MHz on ZYNQ XC7Z020 FPGA. The suggested processor delivers frequency gains of 19.5% and 24.1% compared to the existing implementations. The results demonstrate the usefulness of the proposed architectural changes to improve the processor throughput, timing closure and overall FPGA implementation performance.