Voltage-Aware Optimization of a 16-Transistor Radiation-Hardened SRAM Cell for Low-Power and Reliable Operation in 16 nm CMOS Technology

Abstract

Aggressive scaling of CMOS technology into the 16 nm regime has intensified the long-standing conflict between low-power operation and radiation robustness in embedded Static Random Access Memory (SRAM), particularly for aerospace, defense, and deep-space electronics in which soft errors such as single-event upsets (SEUs) threaten data integrity. While numerous radiation-hardening-by-design (RHBD) topologies have been proposed to mitigate such errors, the majority rely on increasing transistor count or layout redundancy, which inflates area and power overhead without directly addressing the underlying trade-off among critical charge (Qcrit), static noise margin (SNM), leakage current, and delay. This work develops a voltage-aware optimization framework for a proposed 16-transistor (16T) radiation-hardened SRAM cell, implemented using 16 nm CMOS Predictive Technology Model (PTM) transistors within the HSPICE simulation environment. The cell integrates redundant storage nodes, decoupled read/write access paths, and dedicated upset-recovery transistors to suppress single- and multi-node upsets. Supply voltage was swept from 0.5 V to 1.0 V, and read delay, write delay, leakage current, SNM, Qcrit, and power-delay product (PDP) were extracted to characterize the cell across its operating range. Results show that leakage current and PDP rise sharply beyond 0.8 V due to intensified subthreshold conduction, whereas SNM and Qcrit increase monotonically with VDD, confirming improved radiation hardness at higher supply levels. The moderate-voltage region (0.6-0.8 V) is identified as the optimal operating band, balancing speed, leakage, stability, and radiation tolerance without increasing transistor count or circuit area. These findings provide practical guidance for voltage-aware SRAM design in radiation-prone, energy-constrained nanoscale CMOS systems, with future work targeting layout-level, parasitic-aware, and experimental irradiation validation of the proposed architecture.