Stage-Aware Approximate Wallace Tree Multiplier for High-Speed and Low-Power VLSI Systems

Abstract

High-performance and energy-efficientmultipliers are essential components in modern digital signal processing and error-tolerant computing systems. Wallace tree multipliers are popular because they have less partial product accumulation delay, but with the use of exact arithmetic units, they consume much power and hardware overhead. To overcome this drawback, it is proposed in this paper that a stage-aware approximate Wallace tree multiplier is used, which selectively uses approximation. to the various stages of reduction in order to attain a better accuracy-efficiency trade-off. The proposed design uses aggressive approximate full adders in early error-resilient phases, moderate approximate full adders in middle phases and exact full adders in error-sensitive phases, rather than the more traditional approximate multipliers which use a fixed approximation strategy to retain accuracy in the final accumulation with an exact Kogge-Stone adder. The suggested 8x8 multiplier architecture is developed in Verilog and tested with the help of functional simulation and post-synthesis analysis in Xilinx Vivado on Artix-7 FPGA. Performance results show large improvements of logic complexity, power consumption and critical path delay over precise and uniformly approximate Wallace tree multipliers. Analysis of the errors obtained with the help of a special simulation model verifies that, despite the large error rate inherent to the design because of the approximation at an early stage, the average distance to the error is bounded, which means that most errors occur in the lower-level bits of significance. Such findings confirm the performance of the stage-wise approximation method and emphasize the appropriateness of the use of the suggested multiplier in error-tolerant domains, including multimedia processing and machine learning accelerators.