Logic-Correlated Static Timing Analysis

Abstract

Traditional Static Timing Analysis (STA) has largely remained functionally agnostic. Industry‑standard STA tools generally fail to resolve functional correlations across multiple levels of logical gating. Functionality‑aware STA reduces the analytical burden, but standard flows must enable all timing arcs because arrival delay differences across arcs can cause functional race conditions, manifesting as functional glitches and crosstalk. These glitches and crosstalk‑induced delays significantly impact both timing and power integrity. In addition, arc‑based STA introduces excessive pessimism and computational overhead during timing updates. In sub‑10nm technologies, where timing signoff is sensitive to even minor pessimism, more refined methods are required. A block‑based STA methodology is presented that works alongside arc‑based analysis to reduce pessimism in timing, crosstalk, dynamic power, and EMIR analyses. The method captures arrival times at all input pins of combinational gates or logic building blocks (LBBs). By evaluating the relationships between these arrival times and the functional behavior of the logic, the engine dynamically determines which arcs should be enabled for accurate edge propagation.