A COMPREHENSIVE REVIEW OF CMOS LOW-NOISE AMPLIFIERS FOR SUB-6 GHz WIRELESS RECEIVERS

Abstract

The low-noise amplifier (LNA), as the first Component of wireless receiver after an antenna, plays a crucial role in deciding the receiver sensitivity, noise figure (NF), gain, linearity, and dynamic range. The evolution of sub-6 GHz wireless systems toward 5G New Radio (NR), Wi-Fi, SAW-less front ends, and IoT has imposed strict and often conflicting requirements for LNA design. This paper reviews major CMOS LNA architectures and their performance trade-offs, with highlighting on linearity enhancement techniques. Previously reported linearization methods were systematically classified into five major categories (a) feedback, (b) feedforward, (c) derivative superposition (DS) including CDS, (d) noise/distortion cancellation, and (e) post distortion. Their effectiveness in suppressing 2nd & 3rd order nonlinearities and improving linearity (IIP2/IIP3) is comparatively discussed. Attention is given to nonlinear transconductance () and output conductance ()  and deep-submicron CMOS limitations. Recent sub-6 GHz implementations are reviewed to evaluate trade-offs among gain, NF, linearity, bandwidth, power, and area. Finally, key research challenges and future directions toward highly linear, low-noise, wideband, and power-efficient CMOS LNAs are identified.