A Pipelined Fixed-Point FPGA Architecture for Binary Antilogarithmic Computation Using Leading-One Detection and BIST

Abstract

This paper presents a novel FPGA-based architecture for computing the binary antilogarithm of 16-bit fixed-point numbers, comprising both integer and fractional components. The proposed design employs a two-dimensional pipelined architecture integrating modular Processing Elements (PEs) and a long Bit Vector (BV), which is efficiently partitioned into smaller sub-vectors. This partitioning minimizes the impact of long interconnects, thereby enhancing the overall clock frequency and throughput. A key feature of the architecture is the utilization of a leading-one detection circuit, which streamlines the antilogarithmic computation process by enabling fast normalization and exponent extraction. To further improve the reliability and robustness of the design, a Built-In Self-Test (BIST) mechanism is integrated into the architecture. The BIST system facilitates on-chip error detection and correction, ensuring error-free output during runtime and post-deployment scenarios. The architecture demonstrates scalability, modularity, and high performance, making it suitable for real-time signal processing and embedded system applications requiring fast and accurate fixed-point binary antilogarithmic operations. In terms of register usage, the proposed design uses 540 registers, demonstrating minimal resource consumption in comparison to the floating-point (1300) and LUT-based (800) implementations, though the fixed-point variant is slightly higher at 620. When evaluating power consumption, the proposed system is also efficient, drawing only 105 mW, which is the lowest among all methods. Overall, the proposed pipelined fixed-point FPGA architecture with LOD and BIST demonstrates clear advantages in speed, resource efficiency, and power savings, making it a compelling choice for high-performance, low-power binary antilog computations.