Verification-Driven Architectural Power-Domain Partitioning for Reducing Standby Leakage in Complex System-on-Chip Designs

Abstract

In a system-on-chip program‚ the choice of power-domain boundaries gets made early for reasons that have almost nothing to do with how hard the result will be to verify: a floorplanning constraint‚ a convenient functional grouping‚ a leakage number computed against a tidy activity model‚ will each settle the question before verification gets a seat at the table․ However‚ most implications of the boundary with respect to verification‚ sequencing hazards at domain boundaries‚ and schedule exposure at system bring-up only emerge further on when RTL is frozen and the architecture isn't a variable anyone wants to reopen․ So‚ this argue that partition quality should not be principally measured by leakage savings in isolation‚ but rather by the cost of verification and its impact on bring-up schedule deriving from the combination of growing the legal power-state combinations‚ sequencing risk at domain boundaries‚ and schedule exposure at integration․ A partition minimizing theoretical leakage or multiplying legal states beyond what any verification plan can credibly verify‚ or one that is not verifiable ahead of tape-out for sequencing correctness‚ may be a worse program outcome than a coarser partition that closes cleanly and retains most of the leakage-benefit․ This article proposes a framework based on emulation-based validation and ownership of bring-up risk across chip‚ die‚ macro‚ and subsystem programs‚ based on six evaluation categories: activity affinity‚ dependency structure‚ memory-retention classification‚ wake-latency and software orchestration cost‚ verification-state cost‚ and physical feasibility‚ and uses that framework to assess a four-way memory retention classification embedded in sequencing correctness with power collapse and restoration․ The central case pattern is a generalized coarser verification aware partition that is shown to recover most of the benefit of the leakage-optimal partition while avoiding the verification-state explosion and the related bring-up delay․ The paper examines the literature on leakage reduction circuits‚ verification complexity growth in multi-domain architectures and wake sequencing driven by rush-current․ In the long term‚ verification-cost-blind partitioning is likely to become even more critical‚ since many designs are moving towards chiplet and 3D integration approaches․ The conclusion of this article is that partition quality is determined jointly by leakage‚ verification cost and bring-up risk‚ and that none of these three is a dominating factor․