Rahul Singh Bhadauria, V. Maheshwari, R. Kar, A.K.Bhattacharjee, & D. Manda. (2014). Delay Modelling of On-Chip RC Global VLSI Interconnect for Step Input. International Journal of Computer Information Systems and Industrial Management Applications, 6, 9. Retrieved from https://cspub-ijcisim.org/index.php/ijcisim/article/view/263