VIVEK KUMAR KUSHWAH; ASHUTOSH KUMAR SINGH; KANIKA JINDAL. Low Power Optimization of Hybrid Logic Full Adder Design using FinFET Technology for High-Speed Arithmetic Circuits. International Journal of Computer Information Systems and Industrial Management Applications, [S. l.], v. 18, n. 4s, p. 722–729, 2026. DOI: 10.70917/ijcisim-2026-2561. Disponível em: https://cspub-ijcisim.org/index.php/ijcisim/article/view/2561. Acesso em: 2 jul. 2026.