SUPREETHA RAO; SATISH BHAIRANNAWAR. Optimized Pipelined RISC-V Processor with Data Hazard Detection for Verification of Ethernet Controller . International Journal of Computer Information Systems and Industrial Management Applications, [S. l.], v. 18, n. 19s, p. 1042–1052, 2026. DOI: 10.70917/ijcisim-2026-4546. Disponível em: https://cspub-ijcisim.org/index.php/ijcisim/article/view/4546. Acesso em: 16 sep. 2026.