CHAYA BHAVI; ANURADHA M. SANDI; PRASHANT BACHANNA. A Pipelined Fixed-Point FPGA Architecture for Binary Antilogarithmic Computation Using Leading-One Detection and BIST. International Journal of Computer Information Systems and Industrial Management Applications, [S. l.], v. 18, n. 21s, p. 1703–1721, 2026. DOI: 10.70917/ijcisim-2026-5920. Disponível em: https://cspub-ijcisim.org/index.php/ijcisim/article/view/5920. Acesso em: 7 nov. 2026.