[1]
Vasudeva G., Bharathi Gururaj, Mruthika N., Raghavendra Chinmai S., Sowjanya M. Sharma, and Yashwanth S., “A Survey of AES-256 and SHA-256 Hardware Architectures on FPGA”, IJCISIM, vol. 18, no. 16s, pp. 1480–1489, Aug. 2026.