1.
Vasudeva G., Bharathi Gururaj, Mruthika N., Raghavendra Chinmai S., Sowjanya M. Sharma, Yashwanth S. A Survey of AES-256 and SHA-256 Hardware Architectures on FPGA. IJCISIM [Internet]. 2026 Aug. 12 [cited 2026 Aug. 15];18(16s):1480-9. Available from: https://cspub-ijcisim.org/index.php/ijcisim/article/view/4679