Chaya Bhavi, Anuradha M. Sandi, Prashant Bachanna. A Pipelined Fixed-Point FPGA Architecture for Binary Antilogarithmic Computation Using Leading-One Detection and BIST. IJCISIM [Internet]. 2026 Aug. 28 [cited 2026 Nov. 7];18(21s):1703-21. Available from: https://cspub-ijcisim.org/index.php/ijcisim/article/view/5920