Low Power Optimization of Hybrid Logic Full Adder Design using FinFET Technology for High-Speed Arithmetic Circuits

Abstract

ower efficiency and high computational speed are the necessary requirements in present-day digital processors for use in artificial intelligence hardware, edge computing platforms, and mobile devices. The traditional arithmetic logic circuit designs, based on CMOS transistors, face the issues of having high leakage currents, poor power efficiency, and reduced effectiveness in deep nanometer technology nodes. In this paper, an attempt is made to address the above problem by designing a low power hybrid logic full adder circuit with an approach of Pass Transistor Logic Adder Circuit implemented using FinFET transistors. Better electrostatic control and reduced short channel effect makes FinFET transistors an ideal choice for improving the performance of electronic circuits. Simulations done with HSPICE software show that the proposed adder circuit design outperforms the existing GNRFET technology by achieving 94.8%, 93.6%, 60.2%, 97.9%, and 68.5% improvements in power dissipation, current consumption, propagation delay, power-delay product, and average power dissipation respectively.