Delay Modelling of On-Chip RC Global VLSI Interconnect for Step Input

Abstract

This paper presents an accurate and efficient model to compute the delay metric of on chip high speed VLSI interconnects. The proposed delay metric assumption is based on RC interconnect model. Interconnect has become a dominant factor in deep sub micrometer (DSM) integrated circuit (IC) technology. The Elmore delay has been the metric of choice for the performance driven design applications. But the accuracy of the Elmore delay is insufficient. For optimization like physical synthesis and static timing analysis, efficient interconnect delay computation is critical. In this paper, a delay metric using RC-int and RC-out has been formulated which computes the delay at any arbitrary point on the waveform and at any point along the interconnect line. The proposed model is based on the first three moments of the impulse response. Two pole RC model is developed based on the first, second and third moments’ effect onto the delay calculation for interconnect lines. This two pole approach permits the pre-characterization of the interconnect delay. The empirical D3M metric is shown to be a special case one present here, the accuracy of delay metric is insufficient, the metric also provides an expression for impulse response, we absorbs significant improvement of at least 50% accuracy delay estimate when compared to the Elmore delay and even through our estimate are as ease to compute as Elmore delay, the metric has proven to be accurate to with in 50% of HSPICE simulation. The proposed metric also provides an expression for impulse response. The SPICE simulation results justify the accuracy and efficiency of the proposed model. . The novelty of the work is that it does not require any look-up table for the calculation of the delay.