Department of Physical Education and Kinesiology, National Dong Hwa University, No. 1, Sec. 2, Da Hsueh Rd. Shoufeng, Hualien 97401, Taiwan, R.O.C

Abstract

Network on Chip (NoC) has been introduced as a cost effective solution to address the on chip design challenges of the dedicated bus-based communications for multicore Systems-on-Chip(SoC). The increase in core density for a multicore system and parallel execution of programs over these cores contribute to the multicasting. Multicast communication results in generation of multiple packets from a single source. Routers with input buffers form the backbone of a traditional NoC based communication system. Buffer-less NoCs are gaining popularity due to simplicity in the router design, low power consumption, and less chip area. Considering the cost overhead of the buffer NoCs deflection routers with minimal number of buffers are gaining importance. All architectural enhancement proposed in NoC systems are focusing in input buffered routers. We propose a novel cost effective deflection architecture that facilitates multicast support. We are making use of a partitioning mechanism for the flit duplication. Experimental analysis proves that our technique substantially reduces average transaction latency of multicast packets and link traversal count without increasing the average deflection rate.