Pareto-Optimal Power–Delay Co-Optimization of Advanced CMOS Technologies for Next-Generation VLSI Systems Using NSGA-II

Abstract

Power dissipation and propagation delay are antagonistic design objectives in deeply scaled very-large-scale integration (VLSI): voltage and device downsizing reduce switching energy but weaken drive current, whereas aggressive sizing and low-threshold operation improve speed at the expense of dynamic, short-circuit, and leakage power. This study develops a reproducible Non-dominated Sorting Genetic Algorithm II (NSGA-II) framework for simultaneous power–delay optimization of four representative CMOS technology classes: 45 nm planar CMOS, 22 nm FinFET, 12 nm FinFET, and 5 nm stacked-nanosheet gate-all-around FET (GAAFET). A technology-scaled fan-out-of-four inverter benchmark is parameterized by supply voltage, effective drive size, p/n sizing ratio, threshold voltage, and gate-length bias. The two objectives are to minimize average power of a 1,000-stage switching bank and minimize FO4 propagation delay subject to area, transition-balance, overdrive, and leakage-share constraints. Main searches use 100 individuals for 140 generations; ten independent equal-budget comparisons assess NSGA-II against a weighted-sum genetic algorithm and random search. NSGA-II generated well-distributed fronts and achieved the best average hypervolume (1.16945) and inverted generational distance (0.01916). Knee solutions reduced power and delay from 2.366 mW and 23.041 ps at 45 nm to 0.226 mW and 2.541 ps at 5 nm. Two-thousand-sample process–voltage–temperature analysis confirmed that the selected compromises remain stable, although leakage sensitivity grows in scaled FinFET and GAAFET designs. The framework supplies designers with a set of implementable alternatives rather than a single preference-dependent optimum and is suitable for early technology–circuit co-design before proprietary process-design-kit sign-off.